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| Number of Variables (n) |
Seed (0,1,2,3,4) | Date | Contestants | Computational Resource |
Data | |
|---|---|---|---|---|---|---|
| 1 | 74 | 0 | 2016/12/17 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 2 | 73 | 0 | 2016/12/17 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 3 | 72 | 0 | 2016/12/13 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 4 | 71 | 0 | 2016/12/13 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 5 | 70 | 0 | 2016/12/13 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 6 | 69 | 0 | 2016/12/13 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 7 | 68 | 0 | 2016/12/13 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 8 | 67 | 0 | 2016/12/13 | Antoine Joux | New hybridized XL related algorithm, Heterogeneous cluster of Intel Xeon @ 2.7-3.5 Ghz | Details |
| 9 | 66 | 0 | 2016/01/22 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 10 | 65 | 0 | 2015/12/17 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 11 | 64 | 0 | 2015/12/1 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 12 | 63 | 0 | 2015/11/23 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 13 | 62 | 0 | 2015/11/19 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 14 | 61 | 0 | 2015/05/13 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 15 | 60 | 0 | 2015/05/02 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 16 | 59 | 0 | 2015/04/29 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 17 | 58 | 0 | 2015/04/28 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 64 Spartan 6 FPGAs | Details |
| 18 | 57 | 0 | 2015/04/28 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 64 Spartan 6 FPGAs | Details |
| 19 | 56 | 0 | 2015/04/28 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 64 Spartan 6 FPGAs | Details |
| 20 | 55 | 0 | 2015/04/28 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 64 Spartan 6 FPGAs | Details |
| Ex. | 20 | 0 | 2015/3/20 | Yun-Ju Huang | Magma F4, Intel(R) Xeon(R) CPU E5-4617, 2.90GHz, 1T RAM | Details |
| Number of Variables (n) |
Seed (0,1,2,3,4) | Date | Contestants | Computational Resource |
Data | |
|---|---|---|---|---|---|---|
| 1 | 35 | 2 | 2016/09/09 | Takuma Ito, Shigenori Uchiyama | modified F4 algorithm, Intel(R) Xeon(R) CPU E5-2620 v4, 2.10GHz, 256GB RAM | Details |
| Ex. | 20 | 0 | 2015/3/20 | Yun-Ju Huang | Magma F4, Intel(R) Xeon(R) CPU E5-4617, 2.90GHz, 1T RAM | Details |
| Number of Variables (n) |
Seed (0,1,2,3,4) | Date | Contestants | Computational Resource |
Data | |
|---|---|---|---|---|---|---|
| 1 | 36 | 0 | 2016/07/13 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | XL with block Wiedemann, 4 x AMD Opteron 6282 SE | Details |
| 2 | 35 | 0 | 2015/09/30 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | XL with block Wiedemann, 4 x AMD Opteron 6282 SE | Details |
| 3 | 34 | 0 | 2015/08/04 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | XL with block Wiedemann, 4 x AMD Opteron 6282 SE | Details |
| 4 | 34 | 1 | 2016/08/13 | Takuma Ito, Shigenori Uchiyama | modified F4 algorithm, Intel(R) Xeon(R) CPU E5-2620 v4, 2.10GHz, 256GB RAM | Details |
| Ex. | 20 | 0 | 2015/3/20 | Yun-Ju Huang | Magma F4, Intel(R) Xeon(R) CPU E5-4617, 2.90GHz, 1T RAM | Details |
| Number of Equations (m) |
Seed (0,1,2,3,4) | Date | Contestants | Computational Resource |
Data | |
|---|---|---|---|---|---|---|
| 1 | 66 | 0 | 2015/07/13 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 2 | 65 | 0 | 2015/07/08 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 3 | 64 | 0 | 2015/07/01 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 4 | 63 | 0 | 2015/06/01 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 5 | 62 | 0 | 2015/05/20 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 6 | 61 | 0 | 2015/05/20 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 7 | 60 | 0 | 2015/05/16 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 8 | 59 | 0 | 2015/05/16 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 9 | 58 | 0 | 2015/05/16 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 10 | 57 | 0 | 2015/05/16 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 11 | 56 | 0 | 2015/05/16 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| 12 | 55 | 0 | 2015/05/16 | Tung Chou, Ruben Niederhagen, Bo-Yin Yang | Gray Code enumeration, Rivyera, 128 Spartan 6 FPGAs | Details |
| Ex. | 10 | 0 | 2015/3/20 | Yun-Ju Huang | Magma F4, Intel(R) Xeon(R) CPU E5-4617, 2.90GHz, 1T RAM | Details |
| Number of Equations (m) |
Seed (0,1,2,3,4) | Date | Contestants | Computational Resource |
Data | |
|---|---|---|---|---|---|---|
| 1 | 19 | 4 | 2016/05/12 | Wen-Ding Li, Yun-An Chang, Ming-Shing Chen, Chen-Mou Cheng, Bo-Yin Yang | MiniGB-F4, AMD opteron 6376x4 512GB RAM, AMD opteron 6376x4 512GB RAM | Details |
| 2 | 18 | 0 | 2016/03/11 | Rusydi Makarim, Marc Stevens | M4GB, 2 x Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz, 256GiB RAM | Details |
| 3 | 18 | 4 | 2016/05/06 | Wen-Ding Li, Yun-An Chang, Ming-Shing Chen, Chen-Mou Cheng, Bo-Yin Yang | MiniGB-F4, Intel(R) Xeon(R) CPU E5620 x 8, Intel(R) Xeon(R) CPU E3-1230 v3, Intel(R) Xeon(R) CPU E3-1245 v3 | Details |
| 4 | 17 | 0 | 2016/02/28 | Rusydi Makarim, Marc Stevens | M4GB, 1 x Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz, 128GiB RAM | Details |
| 5 | 16 | 0 | 2015/04/03 | JC Faugere | F5 - FGb, Intel(R) Xeon(R) CPU E5-2670 v2 @ 2.50GHz | Details |
| 6 | 16 | 1 | 2016/02/24 | Rusydi Makarim, Marc Stevens | M4GB, 1 x Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz, 16GiB RAM | Details | Ex. | 10 | 0 | 2015/3/20 | Yun-Ju Huang | Magma F4, Intel(R) Xeon(R) CPU E5-4617, 2.90GHz, 1T RAM | Details |
| Number of Equations (m) |
Seed (0,1,2,3,4) | Date | Contestants | Computational Resource |
Data | |
|---|---|---|---|---|---|---|
| 1 | 19 | 0 | 2016/3/30 | Rusydi Makarim, Marc Stevens | M4GB, 2 x Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz, 256GiB RAM | Details |
| 2 | 18 | 0 | 2016/2/29 | Rusydi Makarim, Marc Stevens | M4GB, 1 x Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz, 128GiB RAM | Details |
| 3 | 17 | 0 | 2016/2/25 | Rusydi Makarim, Marc Stevens | M4GB, 1 x Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz, 128GiB RAM | Details |
| 4 | 16 | 0 | 2015/4/1 | JC Faugere | F5 - FGb, Intel(R) Xeon(R) CPU E5-2670 v2 @ 2.50GHz | Details |
| 5 | 16 | 1 | 2016/2/24 | Rusydi Makarim, Marc Stevens | M4GB, 1 x Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz, 16GiB RAM | Details |
| Ex. | 10 | 0 | 2015/3/20 | Yun-Ju Huang | Magma F4, Intel(R) Xeon(R) CPU E5-4617, 2.90GHz, 1T RAM | Details |